One is a FPGA-based CPU core. It is also a system consisting of the one CPU along with a small number of surrounding peripherals.
It is in an early stage of design.
Here are a few notes on the instruction set.
ld rx, (ry + k)
st rx, (ry + k)
add rx, ry, rz
mov rx, ry
ld rx, #123
b (rx + k)
bl (rx + k)
load/store
ld rx, (ry + k)
ld rx, (++ry + k) [aka pop]
st rx, (ry + k)
st rx, (ry-- + k) [aka push]
ld rx, #k Is this really a mov?
branch
b[cond] (ry + k)
bl[cond] (ry + k)
ALU op
alu3[op] rx, ry, rz [ux, uy]
alu3[op] rx, ry, #k [ux, uy]
alu2[op] rx, ry [ux, uy]
alu2[op] rx, #k [ux] (this is the same as ld (7), or compare)
trap
? trap rx
trap #k
8 registers (including PC) flags (not mapped into register file)
These are special purpose interpretations of more general forms of instruction.
bs = byte-swap
swp = atomically swap *rx and *ry
rti = mov, but also return to user mode. Destination is usually the program counter.
mov upc, rx = rti
mov upc, urx =
mov rx, upc = trap
mov urx, upc =
mov upc, upc =
mov urx, ury = bswap
prefix alternate instruction set
mul => div
signed div
signed mul
rotate => rotate 16 bits
load/store => byte
half-word